;**************************************************************************
;*          K8048  Microchip PIC(tm) Programmer & Experiment board        *
;**************************************************************************
;*          Hardw. Rev: P8048'1          Softw. Rev:  1.02                *
;*          OSC.......: XT 4MHz Max.     POWER.....:  15V DC              *
;**************************************************************************

;==========================================================================
;	Tutor example file: F84_hbridge_pullups.asm
;	Lewis Loflin lewis@bvu.net
;	Related pages:
;	http://www.bristolwatch.com/k150/f84e.htm
;	http://www.bristolwatch.com/k150/f84b.htm
;	http://www.bristolwatch.com/k150/f84a.htm
;	http://www.bristolwatch.com/k150/f84c.htm
;	http://www.bristolwatch.com/k150/f84d.htm	
;==========================================================================

	

;==========================================================================
;
;       Configuration Bits
;
;==========================================================================

_CP_ON                       EQU     H'000F'
_CP_OFF                      EQU     H'3FFF'
_PWRTE_ON                    EQU     H'3FF7'
_PWRTE_OFF                   EQU     H'3FFF'
_WDT_ON                      EQU     H'3FFF'
_WDT_OFF                     EQU     H'3FFB'
_LP_OSC                      EQU     H'3FFC'
_XT_OSC                      EQU     H'3FFD'
_HS_OSC                      EQU     H'3FFE'
_RC_OSC                      EQU     H'3FFF'

	__CONFIG        _CP_OFF & _PWRTE_ON & _WDT_OFF & _XT_OSC 


;==========================================================================
;
;       Register Definitions
;
;==========================================================================

W                            EQU     H'0000'
F                            EQU     H'0001'

;----- Register Files------------------------------------------------------

INDF                         EQU     H'0000'
TMR0                         EQU     H'0001'
PCL                          EQU     H'0002'
STATUS                       EQU     H'0003'
FSR                          EQU     H'0004'
PORTA                        EQU     H'0005'
PORTB                        EQU     H'0006'
EEDATA                       EQU     H'0008'
EEADR                        EQU     H'0009'
PCLATH                       EQU     H'000A'
INTCON                       EQU     H'000B'

OPTION_REG                   EQU     H'0081'
TRISA                        EQU     H'0085'
TRISB                        EQU     H'0086'
EECON1                       EQU     H'0088'
EECON2                       EQU     H'0089'

;----- STATUS Bits --------------------------------------------------------

IRP                          EQU     H'0007'
RP1                          EQU     H'0006'
RP0                          EQU     H'0005'
NOT_TO                       EQU     H'0004'
NOT_PD                       EQU     H'0003'
Z                            EQU     H'0002'
DC                           EQU     H'0001'
C                            EQU     H'0000'

;----- INTCON Bits --------------------------------------------------------

GIE                          EQU     H'0007'
EEIE                         EQU     H'0006'
T0IE                         EQU     H'0005'
INTE                         EQU     H'0004'
RBIE                         EQU     H'0003'
T0IF                         EQU     H'0002'
INTF                         EQU     H'0001'
RBIF                         EQU     H'0000'

;----- OPTION_REG Bits ----------------------------------------------------

NOT_RBPU                     EQU     H'0007'
INTEDG                       EQU     H'0006'
T0CS                         EQU     H'0005'
T0SE                         EQU     H'0004'
PSA                          EQU     H'0003'
PS2                          EQU     H'0002'
PS1                          EQU     H'0001'
PS0                          EQU     H'0000'

;----- EECON1 Bits --------------------------------------------------------

EEIF                         EQU     H'0004'
WRERR                        EQU     H'0003'
WREN                         EQU     H'0002'
WR                           EQU     H'0001'
RD                           EQU     H'0000'

;==========================================================================
;
;       RAM Definition
;
;==========================================================================

        __MAXRAM H'CF'
        __BADRAM H'07', H'50'-H'7F', H'87'

;==========================================================================
;
;       Variables
;
;==========================================================================

;INPUTS
SW1		EQU     H'00'		;SW1 is triggering RA0
SW2		EQU     H'01'		;SW2 is triggering RA1
SW3		EQU     H'02'		;SW3 is triggering RA2
SW4		EQU     H'03'		;SW4 is triggering RA3
;OUTPUTS
LD1		EQU	H'00'		;LD1 is connected to RB0
LD2		EQU	H'01'		;LD2 is connected to RB1
LD3		EQU	H'02'		;LD3 is connected to RB2
LD4		EQU	H'03'		;LD4 is connected to RB3

SW5		EQU H'04'
SW6		EQU H'05'


DELAY_count1	EQU H'0D'
DELAY_count2	EQU H'0E'
DELAY_count3	EQU H'0F'

w_temp        EQU  0x10        ; variable used for context saving 
status_temp   EQU  0x11        ; variable used for context saving


		ORG	0			;Setting Reset vector, reset vector address is 000h in PIC16F84
		GOTO	SETUP			;Jump to RESET procedure when boot-up PIC device.

;*********************************************************************

	ORG     0x004             ; interrupt vector location
	movwf   w_temp            ; save off current W register contents
	movf	STATUS,w          ; move status register into W register
	movwf	status_temp       ; save off contents of STATUS register

; isr code can go here or be located as a call subroutine elsewhere

	MOVLW   0x01 ; PORTB bit to change
	CALL toggle

	BTFSS PORTB, SW5
	GOTO $-1 ; wait for release

	BTFSS PORTB, SW6
	GOTO $-1 ; wait for release

                                                                                                                                                            	CALL DELAY_100mS
	BCF INTCON, RBIF ; CLR IRQ flag

	movf    status_temp,w     ; retrieve copy of STATUS register
	movwf	STATUS            ; restore pre-isr STATUS register contents
	swapf   w_temp,f
	swapf   w_temp,w          ; restore pre-isr W register contents
	retfie                    ; return from interrupt
	

SETUP						;Program starts here !!!		
		
	BSF	STATUS, RP0		    ;Jump to bank 1 of PIC16F84 to access special registers.
	MOVLW	B'00001111'		;Config Port A, Low nibble = Ra0 -> Ra3 are inputs, high nibble not implemented.
	MOVWF	TRISA			;Set I/O configuration for PORTA
	MOVLW	B'11110000'		;Config Port B, Ra7 - RA4 are input, Ra3 - Ra0 are outputs.
	MOVWF	TRISB			;Set I/O configuration for PORTB
	BCF OPTION_REG, NOT_RBPU ; enable PORTB pull ups
	BCF	STATUS,RP0  ;Jump back to bank 0 of PIC.

	CLRF PORTB
	BSF PORTB, SW5 ; pull up on
	BSF PORTB, SW6 ; pull up on

	; interrupt setup
	BSF INTCON, GIE ; global INT enable bit 7
	BSF INTCON, RBIE ; bit 3 ; enable RBPU interrupt
	BCF INTCON, RBIF ; bit 0 ; CLR IRQ flag

	GOTO LOOP

LOOP ;Loop starts here !!!

	BSF PORTB, 3
	CALL DELAY_500mS
	BCF PORTB, 3
	CALL DELAY_500mS

GOTO  LOOP



DELAY_500uS
; the address counter "points" to instruction to be executed
; formula 500uS => DELAY_holdCount1 = (500 - 3)/3 = 166
; time delay = 0 - 771 uS at 4mHz
	MOVLW d'164'
	MOVWF DELAY_count1
	DECFSZ DELAY_count1, f
	GOTO $-1
	RETURN

DELAY_100mS
	MOVLW d'200'
	MOVWF DELAY_count2
	CALL DELAY_500uS
	DECFSZ DELAY_count2
	GOTO $-2
	RETURN

DELAY_500mS
	MOVLW d'5' ; value X 100mS
	MOVWF DELAY_count3
	CALL DELAY_100mS
	DECFSZ DELAY_count3
	GOTO $-2
	RETURN


toggle
  ; a ONE in any bit position will toggle bit(s)
    XORWF   PORTB, F
	RETURN
	




	    END  ;End of source code.


		
		
		
		
		
		
		
		
		
		
		
		
 

	
