Basic NAND gate SR latch circuit.

Basic NAND Gate SR Latch Circuit

by Lewis Loflin

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Here we will learn to build a SR latch from NAND gates. Then we will use that to build a D flip-flop.

74LS00 pin connections and truth table.

A SR latch is a form of a bistable multivibrator. It has two stable states, as indicated by the prefix bi in its name. Typically, one state is referred to as set and the other as reset. The simplest bistable device, therefore, is known as a set-reset, or S-R, latch. To create an S-R latch, we can wire two NAND (or NOR) gates in such a way that the output of one feeds back to the input of another, and vice versa.

Here I will address the NAND gate version.

The Q and not-Q outputs are supposed to be in opposite states. But both forms of SR latches have illegal input states. For a NAND gate latch both inputs LOW turns ON both output LEDs.

Having both S and R equal to 0 is called an invalid or illegal state for the S-R Latch. Otherwise, making S=1 and R=0 "sets" the multivibrator so that Q LED is ON and !Q LED is OFF Conversely, making R HIGH and S LOW "resets" the latch in the opposite state. When S and R NAND latch inputs are both equal to 1, the outputs "latch" in their prior states.

This is opposite for a NOR gate based SR Latch. Both input HIGH turns both LEDs OFF. See Basic NOR Gate SR Latch Circuit.

Ref. Wiki

Basic NAND gate SR latch circuit truth table.

Normally the inputs are left at HIGH, but are normal LOW in the NOR gate version. This created differing input electrical connections.

Here we use two NAND to create a clocked SR Latch. With a 74LS00 the 4 NAND gates allow a single component to be used to create the gated latch. In the NOR gate version we had to use a separate 74LS08 integrated circuit.

Note the truth table. With S and R both HIGH the NAND gates convert this to LOW at A and B. That is still an illegal condition.

SR latch and inverter form D flip-flop.

Above we added an inverter between S and R. This prevents S and R from both being HIGH or LOW. This forms a D flip-flop. Note the following table:

D flip-flop truth table.

Note the change happens when CLK goes LOW to HIGH then LOW. The state of Q and !Q at the H-L transition is stored.

D flip-flop symbol.

Finally if built from NAND or NOR gates the final D flip-flop is identical.

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