Basic NOR gate SR latch circuit.

Tutorial NOR Gate SR Latch Circuit


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Here we will learn the operation of a NOR gate SR latch. From that we will construct a D flip-flop.

Related see the YouTube video NOR Gate SR Latch

A SR latch is a form of a bistable multivibrator. It has two stable states, as indicated by the prefix bi in its name. Typically, one state is referred to as set and the other as reset. The simplest bistable device, therefore, is known as a set-reset, or S-R, latch. To create an S-R latch, we can wire two NOR (or NAND) gates in such a way that the output of one feeds back to the input of another, and vice versa.

Here I will address the NOR gate version.

The Q and not-Q outputs are supposed to be in opposite states. But both forms of SR latches have illegal input states. For a NOR gate latch both input HIGH turns off both output LEDs.

Having both S and R equal to 1 is called an invalid or illegal state for the S-R multivibrator. Otherwise, making S=1 and R=0 "sets" the multivibrator so that Q=1 and not-Q=0. Conversely, making R=1 and S=0 "resets" the multivibrator in the opposite state. When S and R are both equal to 0, the multivibrator's outputs "latch" in their prior states.

This is opposite for a NAND gate based SR Latch. Both input LOW turns both LEDs ON. See Basic NAND Gate SR Latch Circuit.

Ref. Wiki

74LS02 pin connections and truth table.

Compare the above truth table for a 74LS02 to the 74LS00 Quad 2-Input NAND Gates. Both gate types have two inputs, but the outputs differ.

Normally the inputs are left LOW for the NOR gate latch, but are normal HIGH in the NAND gate version. This created differing input electrical connections.

Basic NOR gate gated SR latch circuit truth table.

Above is a gated version of a NOR gate SR latch. We use two 74LS08 AND gates on the inputs. Only when EN goes LOW to HIGH to LOW do we change Q and !Q.

gated SR latch symbol

At this point we have a gated SR Latch. Note the new symbol.



Note in the table two LOW inputs are still illegal even if gated. We will solve this with a D flip-flop.

SR latch and inverter form D flip-flop.

Above we added an inverter between S and R. This prevents S and R from both being HIGH or LOW. The new single input is DIN. This forms a D flip-flop. Note the following table:

D flip-flop truth table.

Note the change happens when CLK goes LOW to HIGH then LOW.

D flip-flop symbol.

Finally if built from NAND or NOR gates the final D flip-flop is identical.



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