Tutorial NOR Gate SR Latch Circuit

by Lewis Loflin

When transitioning from simple combinational logic gates to memory-storing sequential circuits, understanding different gate topologies is crucial. Here we will learn the operation of a NOR gate SR latch. From that foundation, we will examine gated variations and construct a synchronous D flip-flop.

Related see the YouTube video NOR Gate SR Latch

Foundations of the Bistable Multivibrator

An SR latch is a form of a bistable multivibrator. It has two stable states, as indicated by the prefix "bi" in its name. Typically, one state is referred to as "set" and the other as "reset." The simplest bistable device, therefore, is known as a set-reset, or S-R, latch. To create an S-R latch, we can wire two NOR (or NAND) gates in such a way that the output of one feeds back to the input of another, and vice versa. This cross-coupled feedback arrangement locks the circuit into a stable condition until an overriding control signal forces a state change.

Here I will address the NOR gate version, which behaves differently from its NAND gate counterpart regarding resting logic levels and active control states.

Operational Behavior and Truth Table Analysis

The Q and not-Q outputs are supposed to be in opposite, complementary states. But both forms of SR latches have unique illegal input conditions. For a NOR gate latch, holding both inputs HIGH simultaneously turns off both output indicators, destroying the complementary output requirement.

Having both S and R equal to 1 is called an invalid or illegal state for the NOR-based S-R multivibrator because it forces both outputs LOW. Otherwise, making S=1 and R=0 "sets" the multivibrator so that Q=1 and not-Q=0. Conversely, making R=1 and S=0 "resets" the multivibrator into the opposite state. When S and R are both equal to 0, the multivibrator's outputs "latch" in their prior states, preserving memory.

This operational logic is the direct opposite of a NAND gate based SR Latch, where both inputs held LOW turn both outputs ON and resting inputs are kept HIGH. See my comparative tutorial on the Basic NAND Gate SR Latch Circuit.

Normally, the resting inputs for a NOR gate latch are left LOW, whereas they are normally HIGH in the NAND gate version. This creates differing input electrical connections and interface requirements.

Gated NOR Latches and D Flip-Flops

To control when data enters the latch, we can build a gated version of a NOR gate SR latch. By utilizing external logic—such as two 74LS08 AND gates on the inputs—we can regulate when the set and reset signals reach the cross-coupled NOR structure. Only when the enable (EN) line goes active do we permit changes to Q and !Q.

However, even in a gated configuration, two HIGH inputs remain illegal. We solve this limitation by adding an inverter between S and R, transforming the circuit into a single-input D flip-flop where DIN controls data flow. Changes are safely stored during clock transitions, and whether built from NAND or NOR gates at the gate level, the final functional D flip-flop behaves identically.

Fig. 1: Basic NOR gate SR latch circuit.